PIC16F785
TABLE 2-4:
PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx 22,114
xxxx xxxx 49,114
0000 0000 21,114
0001 1xxx 15,114
xxxx xxxx 22,114
--x0 x000 35,114
xx00 ---- 42,114
00xx 0000 45,114
TMR0
PCL
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
FSR
Indirect Data Memory Address Pointer
PORTA(1)
PORTB(1)
PORTC(1)
—
—
—
RA5
RB5
RC5
RA4
RB4
RC4
RA3
—
RA2
—
RA1
—
RA0
—
RB7
RB6
RC6
RC7
RC3
RC2
RC1
RC0
Unimplemented
Unimplemented
—
—
—
—
—
—
PCLATH
INTCON
—
—
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000 21,114
0000 0000 17,114
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
PWMCON1
PWMCON0
PWMCLK
PWMPH1
PWMPH2
—
—
PRSEN
PWMASE
POL
COMOD1 COMOD0 CMDLY4
CMDLY3
SYNC1
PER3
PH3
CMDLY2
SYNC0
PER2
PH2
CMDLY1
PH2EN
PER1
PH1
CMDLY0 -000 0000 100,115
PASEN
PWMP1
C2EN
BLANK2
PWMP0
C1EN
BLANK1
PER4
PH4
PH1EN
PER0
PH0
0000 0000 93,115
0000 0000 94,115
0000 0000 95,115
0000 0000 96,115
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
CM1CON0
CM2CON0
CM2CON1
OPA1CON
OPA2CON
—
C1ON
C2ON
C1OUT
C1OE
C2OE
—
C1POL
C2POL
—
C1SP
C2SP
—
C1R
C2R
—
C1CH1
C2CH1
T1GSS
—
C1CH0
C2CH0
0000 0000 65,115
0000 0000 67,115
C2OUT
MC2OUT
—
MC1OUT
OPAON
OPAON
C2SYNC 00-- --10 68,115
—
—
—
—
—
—
0--- ---- 76,115
0--- ---- 76,115
—
—
—
—
—
—
Unimplemented
Unimplemented
—
—
—
—
—
Legend:
Note 1:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
© 2005 Microchip Technology Inc.
Preliminary
DS41249B-page 13
MICROCHIP [ MICROCHIP ]
