PIC16F631/677/685/687/689/690
TABLE 2-3:
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 2
100h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
xxxx ----
xxxx xxxx
—
44,201
81,201
44,201
36,201
44,201
59,201
69,201
76,201
—
101h TMR0
102h PCL
Program Counter’s (PC) Least Significant Byte
103h STATUS
104h FSR
105h PORTA(4)
106h PORTB(4)
107h PORTC(4)
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
RA5
RB5
RC5
RA4
RB4
RC4
RA3
—
RA2
—
RA1
—
RA0
—
RB7
RB6
RC6
RC7
RC3
RC2
RC1
RC0
108h
109h
—
—
Unimplemented
Unimplemented
—
—
—
10Ah PCLATH
10Bh INTCON
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
44,201
38,201
GIE
PEIE
T0IE
INTE
RABIE
EEDAT3
EEADR3
T0IF
INTF
RABIF(1) 0000 000x
EEDAT
EEADR
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT2
EEADR2
EEDAT1
EEADR1
EEDAT0 0000 0000 120,202
EEADR0 0000 0000 120,202
10Ch
EEADR7(3) EEADR6 EEADR5 EEADR4
10Dh
10Eh EEDATH(2)
10Fh EEADRH(2)
—
—
—
--00 0000 120,202
---- 0000 120,202
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
EEADRH3 EEADRH2 EEADRH1 EEADRH0
—
—
—
110h
111h
112h
113h
114h
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
115h WPUB
116h IOCB
WPUB7
IOCB7
WPUB6
IOCB6
WPUB5
IOCB5
WPUB4
IOCB4
—
—
—
—
—
—
—
—
1111 ----
0000 ----
—
70,202
70,202
—
117h
—
Unimplemented
118h VRCON
119h CM1CON0
11Ah CM2CON0
11Bh CM2CON1
C1VREN
C1ON
C2VREN
VRR
C1OE
C2OE
—
VP6EN
C1POL
C2POL
—
VR3
—
VR2
C1R
C2R
—
VR1
VR0
0000 0000 106,202
C1OUT
C2OUT
C1CH1
C2CH1
T1GSS
C1CH0
C2CH0
0000 -000
0000 -000
98,202
99,202
C2ON
—
MC1OUT MC2OUT
Unimplemented
—
C2SYNC 00-- --10 101,202
11Ch
11Dh
—
—
—
—
—
Unimplemented
—
11Eh ANSEL
11Fh ANSELH(3)
ANS7
—
ANS6
—
ANS5
—
ANS4
—
ANS3(3)
ANS11
ANS2(3)
ANS10
ANS1
ANS9
ANS0
ANS8
1111 1111
---- 1111
61,202
115,202
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
3:
4:
PIC16F685/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
DS41262D-page 34
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
