PIC16F631/677/685/687/689/690
TABLE 2-1:
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
xxxx ----
xxxx xxxx
—
44,201
81,201
44,201
36,201
44,201
59,201
69,201
76,201
—
TMR0
PCL
Program Counter’s (PC) Least Significant Byte
STATUS
FSR
PORTA(7)
PORTB(7)
PORTC(7)
—
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
RA5
RB5
RC5
RA4
RB4
RC4
RA3
—
RA2
—
RA1
—
RA0
—
RB7
RB6
RC6
RC7
RC3
RC2
RC1
RC0
Unimplemented
Unimplemented
—
—
—
—
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
44,201
38,201
41,201
42,201
86,201
86,201
GIE
—
PEIE
ADIF(4)
C2IF
T0IE
INTE
TXIF(2)
EEIF
RABIE
T0IF
INTF
RABIF(1) 0000 000x
RCIF(2)
C1IF
SSPIF(5) CCP1IF(3) TMR2IF(3) TMR1IF -000 0000
0Dh PIR2
OSFIF
—
—
—
—
0000 ----
xxxx xxxx
xxxx xxxx
0Eh TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
10h
11h
12h
13h
14h
T1CON
TMR2(3)
T2CON(3)
SSPBUF(5)
SSPCON(5, 6)
T1GINV
Timer2 Module Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
88,201
91,201
92,201
178,201
177,201
0000 0000
—
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx
SSPM0 0000 0000
xxxx xxxx
SSPM2
SSPM1
15h
16h
17h
18h
19h
CCPR1L(3)
CCPR1H(3)
CCP1CON(3)
RCSTA(2)
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
128,201
128,201
127,201
xxxx xxxx
P1M1
SPEN
P1M0
RX9
DC1B1
SREN
DC1B0
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 0000
—
159,201
151
TXREG(2)
EUSART Transmit Data Register
EUSART Receive Data Register
Unimplemented
1Ah RCREG(2)
154
1Bh
1Ch
1Dh
—
—
PWM1CON(3)
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
144,201
ECCPAS(3)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
A/D Result Register High Byte
PSSAC0
PSSBD1
PSSBD0 0000 0000
141,201
115,201
113,201
1Eh ADRESH(4)
xxxx xxxx
1Fh
ADCON0(4)
ADFM
VCFG
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
3:
4:
5:
6:
PIC16F687/PIC16F689/PIC16F690 only.
PIC16F685/PIC16F690 only.
PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-3 for more detail.
7:
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
DS41262D-page 32
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
