PIC16F631/677/685/687/689/690
TABLE 2-2:
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
44,201
37,201
44,201
81h
OPTION_REG RABPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
82h
PCL
83h
84h
85h
86h
87h
88h
89h
STATUS
FSR
PD
Z
DC
C
0001 1xxx
xxxx xxxx
--11 1111
1111 ----
1111 1111
—
36,201
44,201
59,201
70,202
76,201
—
TRISA
TRISB
TRISC
—
—
—
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
TRISA3
—
TRISA2
—
TRISA1
—
TRISA0
—
TRISB7
TRISC7
TRISB6
TRISC6
TRISC3
TRISC2
TRISC1
TRISC0
Unimplemented
Unimplemented
—
—
—
—
8Ah PCLATH
8Bh INTCON
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
44,201
38,201
GIE
PEIE
T0IE
INTE
RABIE
T0IF
INTF
RABIF(1)
8Ch PIE1
8Dh PIE2
8Eh PCON
—
OSFIE
—
ADIE(4)
C2IE
—
RCIE(2)
C1IE
TXIE(2)
EEIE
SSPIE(5) CCP1IE(3) TMR2IE(3) TMR1IE
-000 0000
0000 ----
--01 --qq
-110 q000
---0 0000
—
39,202
40,202
43,202
48,202
52,202
—
—
—
—
—
—
ULPWUE SBOREN
—
POR
LTS
BOR
SCS
TUN0
8Fh
90h
91h
92h
93h
OSCCON
OSCTUNE
—
—
IRCF2
—
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
HTS
TUN2
—
TUN1
Unimplemented
PR2(3)
Timer2 Period Register
1111 1111
0000 0000
91,202
184,202
SSPADD(5, 7)
Synchronous Serial Port (I2C mode) Address Register
93h
94h
95h
96h
97h
SSPMSK(5, 7)
SSPSTAT(5)
WPUA(6)
MSK7
SMP
—
MSK6
CKE
—
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
1111 1111
0000 0000
--11 -111
--00 0000
187,202
176,202
62,202
WPUA5
IOCA5
—
WPUA4
IOCA4
—
WPUA2
IOCA2
WPUA1
IOCA1
WPUA0
IOCA0
IOCA
—
—
IOCA3
62,202
WDTCON
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
209,202
98h
99h
TXSTA(2)
SPBRG(2)
CSRC
BRG7
TX9
TXEN
BRG5
BRG13
—
SYNC
BRG4
BRG12
SCKP
SENDB
BRG3
BRGH
BRG2
BRG10
—
TRMT
BRG1
BRG9
WUE
TX9D
BRG0
BRG8
ABDEN
0000 0010
0000 0000
0000 0000
01-0 0-00
158,202
161,202
161,202
160,202
BRG6
BRG14
RCIDL
9Ah SPBRGH(2)
9Bh BAUDCTL(2)
BRG15
ABDOVF
BRG11
BRG16
9Ch
9Dh
—
—
Unimplemented
Unimplemented
—
—
—
—
9Eh ADRESL(4)
A/D Result Register Low Byte
ADCS2 ADCS1
xxxx xxxx
-000 ----
115,202
114,202
9Fh
ADCON1(4)
—
ADCS0
—
—
—
—
Legend:
Note 1:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
3:
4:
5:
6:
7:
PIC16F687/PIC16F689/PIC16F690 only.
PIC16F685/PIC16F690 only.
PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
Accessible only when SSPCON register bits SSPM<3:0> = 1001.
© 2007 Microchip Technology Inc.
DS41262D-page 33
MICROCHIP [ MICROCHIP ]
