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PIC16F688-I/ST 参数 Datasheet PDF下载

PIC16F688-I/ST图片预览
型号: PIC16F688-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 202 页 / 3832 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
10.4.1.5  
Synchronous Master Reception  
10.4.1.8  
Synchronous Master Reception Set-  
up:  
Data is received at the RX/DT pin. The RX/DT and TX/  
CK pin output drivers are automatically disabled when  
the EUSART is configured for synchronous master  
receive operation.  
1. Initialize the SPBRGH, SPBRG register pair for  
the appropriate baud rate. Set or clear the  
BRGH and BRG16 bits, as required, to achieve  
the desired baud rate.  
In Synchronous mode, reception is enabled by setting  
either the Single Receive Enable bit (SREN of the  
RCSTA register) or the Continuous Receive Enable bit  
(CREN of the RCSTA register).  
2. Enable the synchronous master serial port by  
setting bits SYNC, SPEN and CSRC.  
3. Ensure bits CREN and SREN are clear.  
4. If using interrupts, set the GIE and PEIE bits of  
the INTCON register and set RCIE.  
When SREN is set and CREN is clear, only as many  
clock cycles are generated as there are data bits in a  
single character. The SREN bit is automatically cleared  
at the completion of one character. When CREN is set,  
clocks are continuously generated until CREN is  
cleared. If CREN is cleared in the middle of a character  
the CK clock stops immediately and the partial charac-  
ter is discarded. If SREN and CREN are both set, then  
SREN is cleared at the completion of the first character  
and CREN takes precedence.  
5. If 9-bit reception is desired, set bit RX9.  
6. Start reception by setting the SREN bit or for  
continuous reception, set the CREN bit.  
7. Interrupt flag bit RCIF will be set when reception  
of a character is complete. An interrupt will be  
generated if the enable bit RCIE was set.  
8. Read the RCSTA register to get the ninth bit (if  
enabled) and determine if any error occurred  
during reception.  
To initiate reception, set either SREN or CREN. Data is  
sampled at the RX/DT pin on the trailing edge of the  
TX/CK clock pin and is shifted into the Receive Shift  
Register (RSR). When a complete character is  
received into the RSR, the RCIF bit is set and the char-  
acter is automatically transferred to the two character  
receive FIFO. The Least Significant eight bits of the top  
character in the receive FIFO are available in RCREG.  
The RCIF bit remains set as long as there are un-read  
characters in the receive FIFO.  
9. Read the 8-bit received data by reading the  
RCREG register.  
10. If an overrun error occurs, clear the error by  
either clearing the CREN bit of the RCSTA  
register or by clearing the SPEN bit which resets  
the EUSART.  
10.4.1.6  
Receive Overrun Error  
The receive FIFO buffer can hold two characters. An  
overrun error will be generated if a third character, in its  
entirety, is received before RCREG is read to access  
the FIFO. When this happens the OERR bit of the  
RCSTA register is set. Previous data in the FIFO will  
not be overwritten. The two characters in the FIFO  
buffer can be read, however, no additional characters  
will be received until the error is cleared. The OERR bit  
can only be cleared by clearing the overrun condition.  
If the overrun error occurred when the SREN bit is set  
and CREN is clear then the error is cleared by reading  
RCREG. If the overrun occurred when the CREN bit is  
set then the error condition is cleared by either clearing  
the CREN bit of the RCSTA register or by clearing the  
SPEN bit which resets the EUSART.  
10.4.1.7  
Receiving 9-bit Characters  
The EUSART supports 9-bit character reception. When  
the RX9 bit of the RCSTA register is set the EUSART  
will shift 9-bits into the RSR for each character  
received. The RX9D bit of the RCSTA register is the  
ninth, and Most Significant, data bit of the top unread  
character in the receive FIFO. When reading 9-bit data  
from the receive FIFO buffer, the RX9D data bit must  
be read before reading the 8 Least Significant bits from  
the RCREG.  
© 2007 Microchip Technology Inc.  
DS41203D-page 105  
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