PIC16F688
10.4.2.3
EUSART Synchronous Slave
Reception
10.4.2.4
Synchronous Slave Reception Set-
up:
The operation of the Synchronous Master and Slave
modes is identical (Section 10.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
• SREN bit, which is a “don’t care” in Slave mode
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCTL ABDOVF RCIDL
—
SCKP
INTE
C2IE
BRG16
RAIE
—
WUE
INTF
TXIE
TXIF
ABDEN 01-0 0-00 01-0 0-00
INTCON
PIE1
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
GIE
EEIE
EEIF
PEIE
ADIE
ADIF
T0IE
RCIE
RCIF
T0IF
RAIF
C1IE
OSFIE
OSFIF
TMR1IE
TMR1IF
PIR1
C2IF
C1IF
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
EUSART Receive Data Register
SPEN
BRG7
BRG15
—
RX9
BRG6
BRG14
—
SREN
BRG5
CREN
BRG4
ADDEN
BRG3
FERR
BRG2
OERR
BRG1
BRG9
TRISC1
RX9D
BRG0
BRG8
TRISC0
BRG13
TRISC5
BRG12
TRISC4
BRG11
TRISC3
BRG10
TRISC2
--11 1111
--11 1111
TXREG
TXSTA
Legend:
EUSART Transmit Data Register
CSRC TX9 TXEN
0000 0000 0000 0000
0000 0010 0000 0010
SYNC
SENDB
BRGH
TRMT
TX9D
x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
DS41203D-page 108
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
