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PIC16F688-I/ST 参数 Datasheet PDF下载

PIC16F688-I/ST图片预览
型号: PIC16F688-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 202 页 / 3832 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
FIGURE 10-8:  
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP  
Q4  
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3  
Q1  
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4  
Auto Cleared  
OSC1  
Bit Set by User  
WUE bit  
RX/DT Line  
Note 1  
RCIF  
Cleared due to User Read of RCREG  
Sleep Command Executed  
Sleep Ends  
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is  
still active. This sequence should not depend on the presence of Q clocks.  
2: The EUSART remains in Idle while the WUE bit is set.  
10.3.3  
BREAK CHARACTER SEQUENCE  
10.3.4  
RECEIVING A BREAK CHARACTER  
The EUSART module has the capability of sending the  
special Break character sequences that are required by  
the LIN bus standard. A Break character consists of a  
Start bit, followed by 12 ‘0’ bits and a Stop bit.  
The Enhanced EUSART module can receive a Break  
character in two ways.  
The first method to detect a Break character uses the  
FERR bit of the RCSTA register and the Received data  
as indicated by RCREG. The Baud Rate Generator is  
assumed to have been initialized to the expected baud  
rate.  
To send a Break character, set the SENDB and TXEN  
bits of the TXSTA register. The Break character trans-  
mission is then initiated by a write to the TXREG. The  
value of data written to TXREG will be ignored and all  
0’s will be transmitted.  
A Break character has been received when;  
• RCIF bit is set  
• FERR bit is set  
• RCREG = 00h  
The SENDB bit is automatically reset by hardware after  
the corresponding Stop bit is sent. This allows the user  
to preload the transmit FIFO with the next transmit byte  
following the Break character (typically, the Sync  
character in the LIN specification).  
The second method uses the Auto-Wake-up feature  
described in Section 10.3.2 “Auto-Wake-up on  
Break”. By enabling this feature, the EUSART will  
sample the next two transitions on RX/DT, cause an  
RCIF interrupt, and receive the next data byte followed  
by another interrupt.  
The TRMT bit of the TXSTA register indicates when the  
transmit operation is active or Idle, just as it does during  
normal transmission. See Figure 10-9 for the timing of  
the Break character sequence.  
Note that following a Break character, the user will  
typically want to enable the Auto-Baud Detect feature.  
For both methods, the user can set the ABDEN bit of  
the BAUDCTL register before placing the EUSART in  
Sleep mode.  
10.3.3.1  
Break and Sync Transmit Sequence  
The following sequence will start a message frame  
header made up of a Break, followed by an auto-baud  
Sync byte. This sequence is typical of a LIN bus  
master.  
1. Configure the EUSART for the desired mode.  
2. Set the TXEN and SENDB bits to enable the  
Break sequence.  
3. Load the TXREG with a dummy character to  
initiate transmission (the value is ignored).  
4. Write ‘55h’ to TXREG to load the Sync character  
into the transmit FIFO buffer.  
5. After the Break has been sent, the SENDB bit is  
reset by hardware and the Sync character is  
then transmitted.  
When the TXREG becomes empty, as indicated by the  
TXIF, the next data byte can be written to TXREG.  
© 2007 Microchip Technology Inc.  
DS41203D-page 101  
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