PIC16F688
10.2.1
SAMPLING
10.2 USART Baud Rate Generator
(BRG)
The data on the RC5/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the USART. By default, the BRG operates in
8-bit mode; setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
EXAMPLE 10-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internally generated clock).
FOSC
--------------------------------------------------------------------
=
Desired Baud Rate
64([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
FOSC
---------------------------------------------
Desired Baud Rate
---------------------------------------------
X =
=
– 1
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 10-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 10-1. Typical baud
rates and error values for the various asynchronous
modes are shown in Table 10-2. It may be advanta-
geous to use the high baud rate (BRGH = 1), or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
64
16000000
-----------------------
9600
64
-----------------------
– 1
= [25.042] = 25
16000000
64(25 + 1)
--------------------------
=
Calculated Baud Rate
= 9615
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
Calc. Baud Rate – Desired Baud Rate
--------------------------------------------------------------------------------------------
Error =
Desired Baud Rate
(9615 – 9600)
----------------------------------
=
= 0.16%
9600
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is IDLE
before changing the system clock.
Note:
When BRGH = 1 and BRG16 = 1 then
SPBRGH:SPBRG values ≤ 4 are invalid.
TABLE 10-1: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/USART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH:SPBRG register pair
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 81
MICROCHIP [ MICROCHIP ]
