PIC16F688
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
300
1201
2403
9615
19230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
While the ABD sequence takes place, the USART state
machine is held in IDLE. The RCIF interrupt is set once
the fifth rising edge on RX is detected. The value in the
RCREG needs to be read to clear the RCIF interrupt.
RCREG content should be discarded.
10.2.2
AUTO BAUD RATE DETECT
The EUSART module supports the automatic detection
and calibration of baud rate. This feature is active only
in Asynchronous mode and while the WUE bit is clear.
The automatic baud rate measurement sequence
(Figure 10-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is self-
averaging.
Note 1: If the WUE bit is set with the ABDEN bit,
auto baud rate detection will occur on the
byte following the Break character (see
Section 10.3.4
“Auto-Wake-up
on
In the Auto Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal baud rate generator is used as
a counter to time the bit period of the incoming serial
byte stream.
SYNC Break Character”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some
combinations
of
oscillator
frequency and USART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the Auto Baud Rate Detection
feature.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto Baud Detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus sync character), in order to
calculate the proper bit rate. The measurement takes
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
TABLE 10-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
0
1
FOSC/512
FOSC/128
1
1
0
1
FOSC/128
FOSC/32
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the pre-configured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes, by checking for 00h in
the SPBRGH register. Refer to Table 10-4 for counter
clock rates to the BRG.
Note:
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit
counter, independent of BRG16 setting.
DS41203B-page 84
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
