PIC16F688
FIGURE 9-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC+1
EEADRH,EEADR
PC+3
PC+3
PC+4
PC+5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC+1)
EEDATH,EEDAT
INSTR (PC+3)
INSTR (PC+4)
BSF EECON1,RD
executed here
INSTR(PC-1)
executed here
INSTR(PC+1)
executed here
Forced NOP
executed here
INSTR(PC+3)
executed here
INSTR(PC+4)
executed here
RD bit
EEDATH
EEDAT
Register
EERHLT
TABLE 9-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
all other
Resets
Value on
POR, BOD
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
EEIF
EEIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
C2IF
C2IE
RAIE
C1IF
C1IE
T0IF
INTF
TXIF
TXIE
RAIF 0000 0000 0000 0000
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
--00 0000 0000 0000
0Ch
PIR1
OSFIF
OSFIE
8Ch
97h
PIE1
EEDATH
EEADRH
EEDAT
EEADR
EECON1
EECON2
EEPROM Data register, high byte
98h
EEPROM Address register, high byte
---- 0000 0000 0000
9Ah
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
9Bh
9Ch
9Dh
Legend:
EEPGD
—
—
—
—
—
—
—
WRERR WREN
WR
—
RD
—
---- x000 ---- q000
(1)
—
—
—
—
x= unknown, u= unchanged, - = unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by data EEPROM module.
Note 1: EECON2 is not a physical register.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 75
MICROCHIP [ MICROCHIP ]
