PIC16F688
REGISTER 4-2:
TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h OR 185h)
U-0
—
U-0
—
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
TRISA5
TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
bit 0
bit 7
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bits
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
Note 1: TRISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 4-3:
WPUA – WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0
—
U-0
—
R/W-1
R/W-1
U-0
—
R/W-1
R/W-1
R/W-1
WPUA5
WPUA4
WPUA2
WPUA1
WPUA0
bit 7
bit 0
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WPUA<2:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in output mode
(TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in
the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41203B-page 32
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
