PIC16F688
3.7.1
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC16F688 uses the internal oscillator as the system
clock source. The IRCF bits (OSCCON<6:4>) can be
modified to adjust the internal oscillator frequency
without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
3.7.2
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at
any point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time, a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable
(the OST has timed out). This is identical to
Two-Speed Start-up mode. Once the external
oscillator is stable, the LFINTOSC returns to its role as
the FSCM source.
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 29
MICROCHIP [ MICROCHIP ]
