PIC16F688
If VDD falls below VBOD for greater than parameter
(TBOD) (see Section 14.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOD for less
than parameter (TBOD).
11.4.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the VDD to rise to an acceptable level. A config-
uration bit, PWRTE, can disable (if set) or enable (if
cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Detect is enabled, although it is not required.
On any Reset (Power-on, Brown-out Detect, Watchdog
Timer, etc.), the chip will remain in Reset until VDD rises
above VBOD (see Figure 11-3). The Power-up Timer
will now be invoked, if enabled and will keep the chip in
Reset an additional 64 ms.
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
If VDD drops below VBOD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOD, the Power-up Timer will execute a
64 ms Reset.
• VDD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 14.0
“Electrical Specifications”).
11.4.5
BOD CALIBRATION
The PIC16F688 stores the BOD calibration values in
fuses located in the Calibration Word (2008h). The
Calibration Word is not erased when using the speci-
fied bulk erase sequence in the PIC12F6XX/16F6XX
Memory Programming Specification (DS41204) and
thus, does not require reprogramming.
11.4.4
BROWN-OUT DETECT (BOD)
The BODEN0 and BODEN1 bits in the Configuration
Word register selects one of four BOD modes. Two
modes have been added to allow software or hardware
control of the BOD enable. When BODEN<1:0> = 01,
the SBODEN bit (PCON<4>) enables/disables the
BOD allowing it to be controlled in software. By select-
ing BODEN<1:0>, the BOD is automatically disabled in
Sleep to conserve power and enabled on wake-up. In
this mode, the SBODEN bit is disabled. See
Register 11-1 for the configuration word definition.
Note:
Address 2008h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h-
3FFFh), which can be accessed only during
programming. See PIC12F6XX/16F6XX
Memory
Programming
Specification
(DS41204) for more information.
FIGURE 11-3:
BROWN-OUT SITUATIONS
VDD
VBOD
Internal
Reset
(1)
64 ms
VDD
VBOD
Internal
Reset
< 64 ms
(1)
64 ms
VDD
VBOD
Internal
Reset
(1)
64 ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
DS41203B-page 104
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
