PIC16F688
FIGURE 11-2:
RECOMMENDED MCLR
CIRCUIT
11.4 Power-On Reset
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 14.0 “Electrical Specifi-
cations” for details. If the BOD is enabled, the maxi-
mum rise time specification does not apply. The BOD
circuitry will keep the device in Reset until VDD reaches
VBOD (see Section 11.4.4 “Brown-Out Detect
(BOD)”).
VDD
R1
PIC16F688
1 kΩ (or greater)
MCLR
C1
0.1 µF
(optional, not critical)
Note:
The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss
for a minimum of 100 µs.
11.4.2
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 14.0 “Electrical Specifi-
cations” for details. If the BOD is enabled, the
maximum rise time specification does not apply. The
BOD circuitry will keep the device in Reset until VDD
reaches VBOD (see Section 11.4.4 “Brown-Out
Detect (BOD)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
11.4.1
MCLR
PIC16F688 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss
for a minimum of 100 µs.
It should be noted that a WDT Reset does not drive
MCLR pin low.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 11-2, is suggested.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to VDD and an internal
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 103
MICROCHIP [ MICROCHIP ]
