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PIC16F688-I/P 参数 Datasheet PDF下载

PIC16F688-I/P图片预览
型号: PIC16F688-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 174 页 / 2918 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
11.1 Configuration Bits  
Note:  
Address 2007h is beyond the user program  
memory space. It belongs to the special  
configuration memory space (2000h-  
3FFFh), which can be accessed only during  
programming. See “PIC12F6XX/16F6XX  
Memory Programming Specification”  
(DS41204) for more information.  
The configuration bits can be programmed (read as  
0’), or left unprogrammed (read as ‘1’) to select various  
device configurations as shown in Register 11-1.  
These bits are mapped in program memory location  
2007h.  
REGISTER 11-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)  
FCMEN IESO BODEN1 BODEN0 CPD  
CP  
MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0  
bit 0  
bit 13  
bit 13-12  
bit 11  
Unimplemented: Read as ‘1’  
FCMEN: Fail-Safe Clock Monitor Enabled bit  
1= Fail-Safe Clock Monitor is enabled  
0= Fail-Safe Clock Monitor is disabled  
bit 10  
IESO: Internal External Switchover bit  
1= Internal External Switchover mode is enabled  
0= Internal External Switchover mode is disabled  
(1)  
bit 9-8  
BODEN<1:0>: Brown-out Detect Selection bits  
11= BOD enabled  
10= BOD enabled during operation and disabled in Sleep  
01= BOD controlled by SBODEN bit (PCON<4>)  
00= BOD disabled  
(2)  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2-0  
CPD: Data Code Protection bit  
1= Data memory code protection is disabled  
0= Data memory code protection is enabled  
(3)  
CP: Code Protection bit  
1= Program memory code protection is disabled  
0= Program memory code protection is enabled  
(4)  
MCLRE: RA3/MCLR pin function select bit  
1= RA3/MCLR pin function is MCLR  
0= RA3/MCLR pin function is digital input, MCLR internally tied to VDD  
PWRTE: Power-up Timer Enable bit  
1= PWRT disabled  
0= PWRT enabled  
WDTE: Watchdog Timer Enable bit  
1= WDT enabled  
0= WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)  
FOSC<2:0>: Oscillator Selection bits  
111= RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN  
110= RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN  
101= INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN  
100= INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN  
011= EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN  
010= HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
001= XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
000= LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
Note 1: Enabling Brown-out Detect does not automatically enable Power-up Timer.  
2: The entire data EEPROM will be erased when the code protection is turned off.  
3: The entire program memory will be erased when the code protection is turned off.  
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
DS41203B-page 100  
Preliminary  
2004 Microchip Technology Inc.  
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