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PIC16F688-I/P 参数 Datasheet PDF下载

PIC16F688-I/P图片预览
型号: PIC16F688-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 174 页 / 2918 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F688  
To set up a Synchronous Slave Reception:  
10.5.2  
USART SYNCHRONOUS SLAVE  
RECEPTION  
1. Enable the synchronous master serial port by  
setting bits SYNC and SPEN and clearing bit  
CSRC.  
The operation of the Synchronous Master and Slave  
modes is identical, except in the case of Sleep, or any  
IDLE mode and bit SREN, which is a “don't care” in  
Slave mode.  
2. If interrupts are desired, set enable bit RCIE.  
3. If 9-bit reception is desired, set bit RX9.  
4. To enable reception, set enable bit CREN.  
If receive is enabled by setting the CREN bit prior to  
entering Sleep, then a word may be received. Once the  
word is received, the RSR register will transfer the data  
to the RCREG register; if the RCIE enable bit is set, the  
interrupt generated will wake the chip from Sleep. If the  
global interrupt is enabled, the program will branch to  
the interrupt vector.  
5. Flag bit RCIF will be set when reception is  
complete. An interrupt will be generated if  
enable bit RCIE was set.  
6. Read the RCSTA register to get the 9th bit (if  
enabled) and determine if any error occurred  
during reception.  
7. Read the 8-bit received data by reading the  
RCREG register.  
8. If any error occurred, clear the error by clearing  
bit CREN.  
9. If using interrupts, ensure that the GIE and PEIE  
bits in the INTCON register (INTCON<7:6>) are  
set.  
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION  
Value on  
all other  
Resets  
Value on  
POR, BOD  
Addr  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0Ch PIR1  
EEIF  
ADIF  
RCIF  
C2IF  
C1IF  
OSFIF  
TXIF  
WUE  
TMR1IF 0000 0000  
ABDEN 00-0 0-00  
0000 0000  
0000 0000  
00-0 0-00  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0010  
0000 000X  
0000 0000  
11h BAUDCTL ABDOVF RCIDL  
SCKP BRG16  
12h SPBRGH USART Baud Rate High Generator  
13h SPBRG  
14h RCREG  
15h TXREG  
16h TXSTA  
17h RCSTA  
8Ch PIE1  
USART Baud Rate Generator  
USART Receive Register  
USART Transmit Register  
0000 0000  
0000 0000  
0000 0000  
CSRC  
SPEN  
EEIE  
TX9  
RX9  
ADIE  
TXEN  
SREN CREN ADDEN FERR  
RCIE C2IE C1IE OSFIE  
SYNC SENDB BRGH TRMT  
TX9D  
RX9D  
0000 0010  
0000 000X  
OERR  
TXIE  
TMR1IE 0000 0000  
Legend:  
x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.  
DS41203B-page 98  
Preliminary  
2004 Microchip Technology Inc.  
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