PIC16F631/677/685/687/689/690
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
13.12.3 SSP MASK REGISTER
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a ‘don’t care’.
This register can only be accessed when the appropriate
mode is selected by bits (SSPM<3:0> of SSPCON).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
REGISTER 13-3: SSPMSK: SSP MASK REGISTER(1)
R/W-1
MSK7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
MSK<7:1>: Mask bits
1= The received address bit n is compared to SSPADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1= The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed
through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing
the SSPMSK register.
2: In all other SSP modes, this bit has no effect.
© 2007 Microchip Technology Inc.
DS41262D-page 187
MICROCHIP [ MICROCHIP ]
