PIC16F631/677/685/687/689/690
13.12.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON register is
set. This is an error condition due to the user’s firm-
ware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
FIGURE 13-8:
I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W = 0
Receiving Address
A7 A6 A5 A4 A3 A2
Receiving Data
Receiving Data
ACK
ACK
9
ACK
9
SDA
SCL
A1
7
D2 D1 D0
D4
D3
D7 D6 D5 D4 D3 D2 D1 D0
D7
1
D6 D5
1
2
3
4
5
6
8
9
1
2
3
4
5
6
8
2
3
4
5
6
7
8
7
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS41262D-page 186
© 2007 Microchip Technology Inc.
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