PIC16F631/677/685/687/689/690
13.8 Sleep Operation
13.10 Bus Mode Compatibility
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
Table 13-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 13-1: SPI BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the SSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
13.9 Effects of a Reset
There is also a SMP bit which controls when the data is
sampled.
A Reset disables the SSP module and terminates the
current transfer.
TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION(1)
Value on
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh/
10Bh/18Bh
INTCON
PIR1
GIE
—
PEIE
ADIF
T0IE
INTE
TXIF
RABIE
T0IF
INTF
RABIF 0000 000x 0000 000x
0Ch
RCIF
SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
xxxx xxxx uuuu uuuu
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL SSPOV SSPEN CKP
TRISB7 TRISB6 TRISB5 TRISB4
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
14h
—
—
—
—
1111 ----
1111 ----
1111 1111
86h/186h
87h/187h
8Ch
TRISB
TRISC
PIE1
—
ADIE
CKE
RCIE
D/A
TXIE
P
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
94h
SSPSTAT
SMP
S
R/W
UA
BF
0000 0000 0000 0000
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
© 2007 Microchip Technology Inc.
DS41262D-page 183
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