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PIC16F685-I/SS 参数 Datasheet PDF下载

PIC16F685-I/SS图片预览
型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F631/677/685/687/689/690  
The clock polarity is selected by appropriately  
13.5 Master Mode  
programming the CKP bit of the SSPCON register. This  
then, would give waveforms for SPI communication as  
shown in Figure 13-3, Figure 13-5 and Figure 13-6,  
where the MSB is transmitted first. In Master mode, the  
SPI clock rate (bit rate) is user programmable to be one  
of the following:  
The master can initiate the data transfer at any time  
because it controls the SCK. The master determines  
when the slave (Processor 2, Figure 13-2) is to  
broadcast data by the software protocol.  
In Master mode, the data is transmitted/received as  
soon as the SSPBUF register is written to. If the SPI is  
only going to receive, the SDO output could be  
disabled (programmed as an input). The SSPSR  
register will continue to shift in the signal present on the  
SDI pin at the programmed clock rate. As each byte is  
received, it will be loaded into the SSPBUF register as  
if a normal received byte (interrupts and Status bits  
appropriately set). This could be useful in receiver  
applications as a Line Activity Monitor mode.  
• FOSC/4 (or TCY)  
• FOSC/16 (or 4 • TCY)  
• FOSC/64 (or 16 • TCY)  
• Timer2 output/2 (PIC16F685/PIC16F690 only)  
This allows a maximum data rate (at 40 MHz) of  
10 Mbps.  
Figure 13-3 shows the waveforms for Master mode.  
When the CKE bit is set, the SDO data is valid before  
there is a clock edge on SCK. The change of the input  
sample is shown based on the state of the SMP bit. The  
time when the SSPBUF is loaded with the received  
data is shown.  
FIGURE 13-3:  
SPI MODE WAVEFORM (MASTER MODE)  
Write to  
SSPBUF  
SCK  
(CKP = 0  
CKE = 0)  
SCK  
(CKP = 1  
CKE = 0)  
4 Clock  
Modes  
SCK  
(CKP = 0  
CKE = 1)  
SCK  
(CKP = 1  
CKE = 1)  
SDO  
(CKE = 0)  
bit 6  
bit 6  
bit 2  
bit 2  
bit 5  
bit 5  
bit 4  
bit 4  
bit 1  
bit 1  
bit 0  
bit 0  
bit 7  
bit 7  
bit 3  
bit 3  
SDO  
(CKE = 1)  
SDI  
(SMP = 0)  
bit 0  
bit 7  
Input  
Sample  
(SMP = 0)  
SDI  
(SMP = 1)  
bit 0  
bit 7  
Input  
Sample  
(SMP = 1)  
SSPIF  
Next Q4 Cycle  
after Q2↓  
SSPSR to  
SSPBUF  
DS41262D-page 180  
© 2007 Microchip Technology Inc.  
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