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PIC16F685-I/SS 参数 Datasheet PDF下载

PIC16F685-I/SS图片预览
型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F631/677/685/687/689/690  
8.10.3  
OUTPUT CLAMPED TO VSS  
8.10 Comparator Voltage Reference  
The CVREF output voltage can be set to VSS with no  
power consumption by configuring VRCON as follows:  
The comparator voltage reference module provides an  
internally generated voltage reference for the compara-  
tors. The following features are available:  
• VREN = 0  
• VRR = 1  
• Independent from Comparator operation  
• Two 16-level voltage ranges  
• Output clamped to VSS  
• VR<3:0> = 0000  
This allows the comparator to detect a zero-crossing  
while not consuming additional CVREF module current.  
• Ratiometric with VDD  
• Fixed Reference (0.6)  
8.10.4  
OUTPUT RATIOMETRIC TO VDD  
The VRCON register (Register 8-5) controls the  
Voltage Reference module shown in Figure 8-8.  
The comparator voltage reference is VDD derived and  
therefore, the CVREF output changes with fluctuations in  
VDD. The tested absolute accuracy of the Comparator  
Voltage Reference can be found in Section 17.0  
“Electrical Specifications”.  
8.10.1  
INDEPENDENT OPERATION  
The comparator voltage reference is independent of  
the comparator configuration. Setting the VREN bit of  
the VRCON register will enable the voltage reference.  
8.10.2  
OUTPUT VOLTAGE SELECTION  
The CVREF voltage reference has 2 ranges with 16  
voltage levels in each range. Range selection is  
controlled by the VRR bit of the VRCON register. The  
16 levels are set with the VR<3:0> bits of the VRCON  
register.  
The CVREF output voltage is determined by the following  
equations:  
EQUATION 8-1:  
CVREF OUTPUT VOLTAGE  
VRR = 1 (low range):  
CVREF = (VR<3:0>/24) × VDD  
VRR = 0 (high range):  
CVREF = (VDD/4) +  
(VR<3:0> × VDD/32)  
The full range of VSS to VDD cannot be realized due to  
the construction of the module. See Figure 8-8.  
DS41262D-page 104  
© 2007 Microchip Technology Inc.  
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