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PIC16F685-I/SS 参数 Datasheet PDF下载

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型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F631/677/685/687/689/690  
9.1.3  
ADC VOLTAGE REFERENCE  
9.1  
ADC Configuration  
The VCFG bit of the ADCON0 register provides control  
of the positive voltage reference. The positive voltage  
reference can be either VDD or an external voltage  
source. The negative voltage reference is always  
connected to the ground reference.  
When configuring and using the ADC the following  
functions must be considered:  
• Port configuration  
• Channel selection  
• ADC voltage reference selection  
• ADC conversion clock source  
• Interrupt control  
9.1.4  
CONVERSION CLOCK  
The source of the conversion clock is software  
selectable via the ADCS bits of the ADCON1 register.  
There are seven possible clock options:  
• Results formatting  
9.1.1  
PORT CONFIGURATION  
• FOSC/2  
The ADC can be used to convert both analog and digital  
signals. When converting analog signals, the I/O pin  
should be configured for analog by setting the associated  
TRIS and ANSEL bits. See the corresponding port  
section for more information.  
• FOSC/4  
• FOSC/8  
• FOSC/16  
• FOSC/32  
• FOSC/64  
Note:  
Analog voltages on any pin that is defined  
as a digital input may cause the input  
buffer to conduct excess current.  
• FRC (dedicated internal oscillator)  
The time to complete one bit conversion is defined as  
TAD. One full 10-bit conversion requires 11 TAD periods  
as shown in Figure 9-2.  
9.1.2  
CHANNEL SELECTION  
For correct conversion, the appropriate TAD specification  
must be met. See A/D conversion requirements in  
Section 17.0 “Electrical Specifications” for more  
information. Table 9-1 gives examples of appropriate  
ADC clock selections.  
The CHS bits of the ADCON0 register determine which  
channel is connected to the sample and hold circuit.  
When changing channels, a delay is required before  
starting the next conversion. Refer to Section 9.2  
“ADC Operation” for more information.  
Note:  
Unless using the FRC, any changes in the  
system clock frequency will change the  
ADC clock frequency, which may  
adversely affect the ADC result.  
DS41262D-page 108  
© 2007 Microchip Technology Inc.  
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