PIC16F631/677/685/687/689/690
8.9.2
LATCH OUTPUT
8.9
Comparator SR Latch
The SR<1:0> bits of the SRCON register control the
latch output multiplexers and determine four possible
output configurations. In these four configurations, the
CxOUT I/O port logic is connected to:
The SR Latch module provides additional control of the
comparator outputs. The module consists of a single
SR latch and output multiplexers. The SR latch can be
set, reset or toggled by the comparator outputs. The SR
latch may also be set or reset, independent of
comparator output, by control bits in the SRCON control
register. The SR latch output multiplexers select
whether the latch outputs or the comparator outputs are
directed to the I/O port logic for eventual output to a pin.
• C1OUT and C2OUT
• C1OUT and SR latch Q
• C2OUT and SR latch Q
• SR latch Q and Q
After any Reset, the default output configuration is the
unlatched C1OUT and C2OUT mode. This maintains
compatibility with devices that do not have the SR latch
feature.
8.9.1
LATCH OPERATION
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. Each latch input is connected to
a
The applicable TRIS bits of the corresponding ports
must be cleared to enable the port pin output drivers.
Additionally, the CxOE comparator output enable bits of
the CMxCON0 registers must be set in order to make the
comparator or latch outputs available on the output pins.
The latch configuration enable states are completely
independent of the enable states for the comparators.
comparator output and a software controlled pulse
generator. The latch can be set by C1OUT or the PULSS
bit of the SRCON register. The latch can be reset by
C2OUT or the PULSR bit of the SRCON register. The
latch is reset-dominant, therefore, if both Set and Reset
inputs are high, the latch will go to the Reset state. Both
the PULSS and PULSR bits are self resetting which
means that a single write to either of the bits is all that is
necessary to complete a latch set or reset operation.
FIGURE 8-7:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
SR0
C1OE
PULSS
Pulse
Gen(2)
0
MUX
1
C1OUT (from comparator)
C1SEN
S
Q
(3)
C1OUT pin
SR
Latch
(1)
C2OE
SYNCC2OUT (from comparator)
C2REN
1
MUX
R
Q
(3)
0
C2OUT pin
PULSR
Pulse
SR1
Gen(2)
Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
DS41262D-page 102
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
