PIC12F508/509/16F505
FIGURE 4-3:
PIC12F508 REGISTER
FILE MAP
FIGURE 4-4:
PIC12F509 REGISTER
FILE MAP
FSR<6:5>
File Address
00h
00
01
File Address
(1)
INDF
00h
01h
02h
03h
04h
05h
06h
07h
(1)
20h
INDF
TMR0
PCL
TMR0
PCL
01h
02h
03h
04h
05h
STATUS
FSR
Addresses map
back to
addresses
in Bank 0.
STATUS
FSR
OSCCAL
GPIO
OSCCAL
GPIO
06h
07h
General
Purpose
Registers
General
Purpose
Registers
2Fh
0Fh
10h
30h
General
Purpose
Registers
General
Purpose
Registers
1Fh
1Fh
3Fh
Bank 0
Bank 1
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and FSR
Registers”.
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
FIGURE 4-5:
PIC16F505 REGISTER FILE MAP
FSR<6:5>
00
01
10
11
File Address
00h
(1)
20h
40h
60h
INDF
01h
02h
03h
04h
05h
06h
TMR0
PCL
Addresses map back to
addresses in Bank 0.
STATUS
FSR
OSCCAL
PORTB
PORTC
07h
08h
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
70h
10h
1Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
5Fh
7Fh
Bank 1
Bank 2
Bank 3
Bank 0
Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.
© 2007 Microchip Technology Inc.
Preliminary
DS41236C-page 17
MICROCHIP [ MICROCHIP ]
