PIC12F508/509/16F505
4.0
MEMORY ORGANIZATION
FIGURE 4-1:
The PIC12F508/509/16F505 memories are organized
into program memory and data memory. For devices
with more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using one Status register bit. For the PIC12F509 and
PIC16F505, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F508/509
PC<11:0>
12
Stack Level 1
Stack Level 2
CALL, RETLW
Reset Vector
(1)
0000h
4.1
Program Memory Organization for
the PIC12F508/509
User Memory
Space
The PIC12F508 device has a 10-bit Program Counter
(PC) and PIC12F509 has a 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC12F508, and 1K x 12 (0000h-03FFh) for the
PIC12F509 are physically implemented (see
boundaries will cause a wraparound within the first
512 x 12 space (PIC12F508) or 1K x 12 space
(PIC12F509). The effective Reset vector is a 0000h
(see Figure 4-1). Location 01FFh (PIC12F508) and
location 03FFh (PIC12F509) contain the internal
clock oscillator calibration value. This value should
never be overwritten.
On-chip Program
Memory
512 Word
01FFh
0200h
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
Note 1:
Address 0000h becomes the
effective Reset vector. Location
01FFh, 03FFh (PIC12F508,
PIC12F509) contains the
MOVLW XX
internal oscillator calibration value.
©
2007 Microchip Technology Inc.
Preliminary
DS41236C-page 15
MICROCHIP [ MICROCHIP TECHNOLOGY ]
