PIC16F688
TABLE 2-2:
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
IOCA
EEDATH
EEADRH
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
—
TRISC
—
—
PCLATH
INTCON
PIE1
—
PCON
OSCCON
OSCTUNE
ANSEL
—
—
—
WPUA
(2)
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Page
Name
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
IRP
—
—
INTEDG
RP1
—
—
T0CS
RP0
TRISA5
TRISC5
T0SE
TO
TRISA4
TRISC4
PSA
PD
TRISA3
TRISC3
PS2
Z
TRISA2
TRISC2
PS1
DC
TRISA1
TRISC1
PS0
C
TRISA0
TRISC0
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
—
GIE
EEIE
—
—
—
ANS7
—
PEIE
ADIE
—
IRCF2
—
ANS6
—
T0IE
RCIE
ULPWUE
IRCF1
—
ANS5
Write Buffer for upper 5 bits of Program Counter
INTE
C2IE
SBOREN
IRCF0
TUN4
ANS4
RAIE
C1IE
—
OSTS
TUN3
ANS3
T0IF
OSFIE
—
HTS
TUN2
ANS2
INTF
TXIE
POR
LTS
TUN1
ANS1
RAIF
(3)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
—
--11 1111
—
—
---0 0000
0000 000x
0000 0000
—
—
—
—
—
—
—
—
TMR1IE
BOR
SCS
TUN0
ANS0
Unimplemented
--01 --qq
-110 x000
---0 0000
1111 1111
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
VREN
EEDAT7
EEADR7
EEPGD
—
—
—
—
—
EEDAT6
EEADR6
—
WPUA5
IOCA5
EEDATH5
—
VRR
EEDAT5
EEADR5
—
WPUA4
IOCA4
EEDATH4
—
—
EEDAT4
EEADR4
—
—
IOCA3
EEDATH3
VR3
EEDAT3
EEADR3
WRERR
WPUA2
IOCA2
EEDATH2
VR2
EEDAT2
EEADR2
WREN
WPUA1
IOCA1
EEDATH1
VR1
EEDAT1
EEADR1
WR
WPUA0
IOCA0
EEDATH0
VR0
EEDAT0
EEADR0
RD
--11 -111
--00 0000
--00 0000
EEADRH3 EEADRH2 EEADRH1 EEADRH0
---- 0000
0-0- 0000
0000 0000
0000 0000
x--- x000
---- ----
xxxx xxxx
—
-000 ----
—
—
EEPROM Control 2 Register (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
—
ADCS2
ADCS1
ADCS0
—
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged,
x
= unknown,
q
= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
DS41203D-page 10
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
