PIC16F688
EQUATION 7-1:
CVREF OUTPUT VOLTAGE
7.10 Comparator Voltage Reference
VRR = 1 (low range):
CVREF = (VR<3:0>/24) × VDD
VRR = 0 (high range):
CVREF = (VDD/4) +
The Comparator Voltage Reference module provides
an internally generated voltage reference for the com-
parators. The following features are available:
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
(VR<3:0> × VDD/32)
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 7-8.
• Ratiometric with VDD
The VRCON register (Figure 7-3) controls the Voltage
Reference module shown in Figure 7-8.
7.10.3
OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
7.10.1
INDEPENDENT OPERATION
• VREN = 0
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
• VRR = 1
• VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
7.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
7.10.4
OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 14.0
“Electrical Specifications”.
The CVREF output voltage is determined by the following
equations:
REGISTER 7-3:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
VREN
U-0
—
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VREN: CVREF Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0>: CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
© 2007 Microchip Technology Inc.
DS41203D-page 63
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