PIC16F688
TABLE 2-4:
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
POR/BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 3
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
190h
191h
192h
193h
194h
195h
196h
19Ah
19Bh
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
20, 117
14, 117
19, 117
13, 117
20, 117
33, 117
—
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
PCL
STATUS
FSR
TRISA
—
Program Counter’s (PC) Least Significant Byte
0000 0000
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
Indirect Data Memory Address Pointer
xxxx xxxx
—
—
—
TRISA5
TRISC5
TRISA4
TRISC4
TRISA3
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
--11 1111
Unimplemented
—
—
TRISC
—
--11 1111
42, 117
—
Unimplemented
Unimplemented
—
—
—
—
—
PCLATH
INTCON
—
—
—
Write Buffer for upper 5 bits of Program Counter
INTE RAIE T0IF INTF
---0 0000
19, 117
15, 117
—
GIE
PEIE
T0IE
RAIF(2)
0000 000x
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
DS41203D-page 12
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
