PIC16F688
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC16F688 has a 13-bit program counter capable
of addressing a 4K x 14 program memory space. Only
the first 4K x 14 (0000h-01FFF) for the PIC16F688 is
physically implemented. Accessing a location above
these boundaries will cause a wraparound within the
first 4K x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
The data memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP0
and RP1 are bank select bits.
RP1
0
0
1
1
RP0
0
1
0
1
→
→
→
→
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F688
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are the General Purpose Registers, implemented
as static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank are mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
Stack Level 8
Reset Vector
0000h
The register file is organized as 256 x 8 in the
PIC16F688. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see
Interrupt Vector
0004h
0005h
2.2.2
SPECIAL FUNCTION REGISTERS
On-chip Program
Memory
01FFh
02000h
Wraps to 0000h-07FFh
1FFFh
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1, 2-2,
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
©
2007 Microchip Technology Inc.
DS41203D-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
