PIC16F8X
TABLE 4-1
REGISTER FILE SUMMARY
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
0Ah
0Bh
EECON1
EECON2
PCLATH
INTCON
INDF
OPTION_
REG
PCL
STATUS
FSR
TRISA
TRISB
(2)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
(2)
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of the Program Counter (PC)
IRP
RP1
RP0
TO
PD
Z
DC
C
---- ----
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---- ----
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---u uuuu
uuuu uuuu
---- ----
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
Indirect data memory address pointer 0
—
RB7
—
RB6
—
RB5
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0/INT
---x xxxx
xxxx xxxx
---- ----
xxxx xxxx
xxxx xxxx
Unimplemented location, read as '0'
EEDATA
EEADR
PCLATH
INTCON
EEPROM data register
EEPROM address register
—
GIE
—
EEIE
—
T0IE
Write buffer for upper 5 bits of the PC
(1)
INTE
RBIE
T0IF
INTF
RBIF
---0 0000
0000 000x
Uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
---- ----
1111 1111
0000 0000
---- ----
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
---- ----
---0 q000
---- ----
---0 0000
0000 000u
Low order 8 bits of Program Counter (PC)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---- ----
Indirect data memory address pointer 0
—
—
—
PORTA data direction register
PORTB data direction register
Unimplemented location, read as '0'
—
—
—
EEIF
WRERR
WREN
WR
RD
---0 x000
---- ----
---0 0000
EEPROM control register 2 (not a physical register)
—
GIE
—
EEIE
—
T0IE
Write buffer for upper 5 bits of the PC
(1)
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
Legend:
x
= unknown,
u
= unchanged.
-
= unimplemented read as '0',
q
= value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never trans-
ferred to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14
©
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
