PIC16F8X
FIGURE 4-1:
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
36
General
Purpose
registers
(SRAM)
2Fh
30h
Mapped
(accesses)
in Bank 0
AFh
B0h
EEDATA
EEADR
PCLATH
INTCON
EECON1
EECON2
(1)
PCLATH
INTCON
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
(1)
REGISTER FILE MAP -
PIC16F83/CR83
File Address
Indirect
addr.
(1)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
FIGURE 4-2:
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
REGISTER FILE MAP -
PIC16F84/CR84
File Address
(1)
Indirect addr.
TMR0
PCL
STATUS
FSR
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON
Indirect
addr.
(1)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
OPTION
PCL
STATUS
FSR
TRISA
TRISB
OPTION
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2
(1)
PCLATH
INTCON
68
General
Purpose
registers
(SRAM)
Mapped
(accesses)
in Bank 0
4Fh
50h
CFh
D0h
7Fh
Bank 0
Bank 1
FFh
7Fh
Bank 0
Bank 1
FFh
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
©
1998 Microchip Technology Inc.
DS30430C-page 13
MICROCHIP [ MICROCHIP TECHNOLOGY ]
