PIC16F8X
4.0
MEMORY ORGANIZATION
FIGURE 4-1:
There are two memory blocks in the PIC16F8X. These
are the program memory and the data memory. Each
block has its own bus, so that access to each block can
occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
PROGRAM MEMORY MAP
AND STACK -
PIC16F83/CR83
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
Reset Vector
User Memory
Space
Peripheral Interrupt Vector
0000h
0004h
1FFh
4.1
Program Memory Organization
1FFFh
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F83 and PIC16CR83, the first 512 x 14
(0000h-01FFh)
are
physically
implemented
(Figure 4-1). For the PIC16F84 and PIC16CR84, the
first 1K x 14 (0000h-03FFh) are physically imple-
mented (Figure 4-2). Accessing a location above the
physically implemented address will cause a wrap-
around. For example, for the PIC16F84 locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK -
PIC16F84/CR84
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
Reset Vector
Peripheral Interrupt Vector
0000h
0004h
User Memory
Space
3FFh
1FFFh
©
1998 Microchip Technology Inc.
DS30430C-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
