PIC16F7X7
REGISTER 10-2:
SSPCON: MSSP CONTROL (SPI MODE) REGISTER 1 (ADDRESS 14h)
R/W-0
WCOL
bit 7
bit 7
WCOL:
Write Collision Detect bit (Transmit mode only)
1
= The SSPBUF register is written while it is still transmitting the previous word.
(Must be cleared in software.)
0
= No collision
SSPOV:
Receive Overflow Indicator bit
SPI Slave mode:
1
= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow.
(Must be cleared in software.)
0
= No overflow
Note:
bit 5
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit 0
bit 6
SSPEN:
Synchronous Serial Port Enable bit
1
= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0
= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
bit 4
CKP:
Clock Polarity Select bit
1
= Idle state for clock is a high level
0
= Idle state for clock is a low level
SSPM3:SSPM0:
Synchronous Serial Port Mode Select bits
0101
= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0100
= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011
= SPI Master mode, clock = TMR2 output/2
0010
= SPI Master mode, clock = F
OSC
/64
0001
= SPI Master mode, clock = F
OSC
/16
0000
= SPI Master mode, clock = F
OSC
/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I
2
C mode only.
bit 3-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
2004 Microchip Technology Inc.
DS30498C-page 95
MICROCHIP [ MICROCHIP TECHNOLOGY ]
