PIC16F7X7
TABLE 18-12: I
2
C™ BUS DATA REQUIREMENTS
Param.
No.
100*
Symbol
T
HIGH
Characteristic
Clock High Time
100 kHz mode
400 kHz mode
SSP module
101*
T
LOW
Clock Low Time
100 kHz mode
400 kHz mode
SSP module
102*
T
R
SDA and SCL Rise 100 kHz mode
Time
400 kHz mode
SDA and SCL Fall
Time
Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Min
4.0
0.6
1.5 T
CY
4.7
1.3
1.5 T
CY
—
20 + 0.1 C
B
—
20 + 0.1 C
B
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
Max
—
—
—
—
—
—
1000
300
300
300
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
400
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
pF
Time the bus must be free
before a new transmission
can start
(Note 1)
(Note 2)
C
B
is specified to be from
10-400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
C
B
is specified to be from
10-400 pF
µs
µs
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Units
µs
µs
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
103*
T
F
90*
91*
106*
107*
92*
109*
110*
T
SU
:
STA
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Start Condition Hold 100 kHz mode
Time
400 kHz mode
Data Input Hold
Time
Data Input Setup
Time
Stop Condition
Setup Time
Output Valid from
Clock
Bus Free Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
C
B
*
Note 1:
2:
Bus Capacitive Loading
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
2
C™ bus device can be used in a Standard mode (100 kHz) I
2
C bus system but
the requirement, T
SU
:
DAT
≥
250 ns, must then be met. This will automatically be the case if the device does
not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line, T
R
max. + T
SU
:
DAT
= 1000 + 250 = 1250 ns
(according to the standard mode I
2
C bus specification), before the SCL line is released.
2004 Microchip Technology Inc.
DS30498C-page 233
MICROCHIP [ MICROCHIP TECHNOLOGY ]
