PIC16F7X7
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1:
Address
Bank 0
00h
(4)
01h
02h
(4)
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on page
Name
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
Timer0 Module Register
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
GIE
PSPIF
(3)
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xx0x 0000
xx00 0000
xxxx xxxx
xxxx xxxx
RE2
TMR0IF
CCP1IF
—
RE1
INT0IF
TMR2IF
CCP3IF
RE0
RBIF
TMR1IF
CCP2IF
---- x000
---0 0000
0000 000x
0000 0000
000- 0-00
xxxx xxxx
xxxx xxxx
TMR1CS TMR1ON
-000 0000
0000 0000
TOUTPS1
CKP
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000
SSPM3
SSPM2
SSPM1
SSPM0
03h
(4)
04h
06h
07h
08h
(5)
(5)
(1,4)
(4)
(4)
05h
09h
—
—
PEIE
ADIF
CMIF
—
—
TMR0IE
RCIF
LVDIF
—
INT0IE
TXIF
—
RE3
RBIE
SSPIF
BCLIF
0Ah
Write Buffer for the upper 5 bits of the Program Counter
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
OSFIF
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
—
WCOL
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN T1SYNC
Timer2 Module Register
TOUTPS3 TOUTPS2
SSPOV
SSPEN
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
—
SPEN
—
RX9
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADDEN
CCP1M2
FERR
CCP1M1
OERR
RX9D
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
CCP1M0
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
AUSART Transmit Data Register
AUSART Receive Data Register
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
—
ADCS1
—
ADCS0
CCP2X
CHS2
CCP2Y
CHS1
CCP2M3
CHS0
CCP2M2
GO/DONE
CCP2M1
CHS3
A/D Result Register High Byte
ADON
CCP2M0
--00 0000
xxxx xxxx
0000 0000
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or
GOTO).
2:
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6:
This bit always reads as a ‘1’.
7:
OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8:
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
DS30498C-page 18
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
