PIC16F7X7
TABLE 2-1:
Address
Bank 1
80h
(4)
81h
82h
84h
86h
87h
88h
(5)
89h
(5)
(1,4)
(4)
(4)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on page
Name
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
SSPCON2
PR2
SSPADD
SSPSTAT
CCPR3L
CCPR3H
CCP3CON
TXSTA
SPBRG
—
ADCON2
CMCON
CVRCON
ADRESL
ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
RBPU
IRP
INTEDG
RP1
T0CS
RP0
T0SE
TO
PSA
PD
PS2
Z
PS1
DC
PS0
C
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
PSPMODE
(5)
INT0IE
TXIE
—
—
IRCF0
TUN4
ACKEN
—
(8)
RBIE
SSPIE
BCLIE
—
OSTS
(7)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
IBF
(5)
—
GIE
PSPIE
—
—
—
GCEN
(3)
83h
(4)
(4)
85h
OBF
(5)
—
PEIE
ADIE
CMIE
—
IRCF2
—
ACKSTAT
IBOV
(5)
—
TMR0IE
RCIE
LVDIE
—
IRCF1
TUN5
ACKDT
2
C™
PORTE Data Direction bits
TMR0IF
CCP1IE
—
SBOREN
IOFS
TUN2
PEN
INT0IF
TMR2IE
CCP3IE
POR
SCS1
TUN1
RSEN
RBIF
TMR1IE
CCP2IE
BOR
SCS0
TUN0
SEN
0000 1111
---0 0000
0000 000x
0000 0000
000- 0-00
---- -1qq
-000 1000
--00 0000
0000 0000
1111 1111
8Ah
Write Buffer for the upper 5 bits of the Program Counter
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
OSFIE
TUN3
RCEN
Timer2 Period Register
Synchronous Serial Port (I
SMP
CKE
mode) Address Register
P
S
R/W
UA
BF
D/A
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
—
CSRC
—
TX9
CCP3X
TXEN
CCP3Y
SYNC
CCP3M3
—
CCP3M2
BRGH
CCP3M1
TRMT
TX9D
CCP3M0
--00 0000
0000 -010
0000 0000
—
—
Baud Rate Generator Register
Unimplemented
—
C2OUT
CVREN
ADFM
—
C1OUT
CVROE
ADCS2
ACQT2
C2INV
CVRR
VCFG1
ACQT1
C1INV
—
VCFG0
ACQT0
CIS
CVR3
PCFG3
—
CM2
CVR2
PCFG2
—
CM1
CVR1
PCFG1
—
CM0
CVR0
PCFG0
--00 0---
0000 0111
000- 0000
xxxx xxxx
A/D Result Register Low Byte
0000 0000
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or
GOTO).
2:
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6:
This bit always reads as a ‘1’.
7:
OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8:
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS30498C-page 19
MICROCHIP [ MICROCHIP TECHNOLOGY ]
