PIC16F7X7
12.7
A/D Operation During Sleep
12.8
Effects of a Reset
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 =
11).
When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the
SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRESH register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a
SLEEP
instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 =
11).
To perform an A/D
conversion in Sleep, ensure the
SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRESH register will contain unknown data after
a Power-on Reset.
12.9
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRESH
to the desired location). The appropriate analog input
channel must be selected and an appropriate acquisi-
tion time should pass before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
TABLE 12-2:
Address
SUMMARY OF A/D REGISTERS
Bit 7
GIE
PSPIF
(1)
OSFIF
PSPIE
(1)
OSFIE
ADCS1
ADFM
RA7
—
IBF
Bit 6
PEIE
ADIF
CMIF
ADIE
CMIE
ADCS0
RA6
—
OBF
Bit 5
TMR0IE
RCIF
LVDIF
RCIE
LVDIE
CHS2
RA5
—
IBOV
Bit 4
INT0IE
TXIF
—
TXIE
—
CHS1
VCFG0
RA4
—
PSPMODE
Bit 3
RBIE
SSPIF
BCLIF
SSPIE
BCLIE
Bit 2
TMR0IF
CCP1IF
—
CCP1IE
—
Bit 1
INT0IF
Bit 0
RBIF
Value on:
POR, BOR
Value on
all other
Resets
Name
0Bh,8Bh,
INTCON
10Bh, 18Bh
0Ch
0Dh
8Ch
8Dh
1Eh
1Fh
9Fh
05h
85h
09h
89h
Legend:
Note 1:
2:
3:
PIR1
PIR2
PIE1
PIE2
ADCON0
ADCON1
PORTA
TRISA
PORTE
(2)
TRISE
(2)
0000 000x 0000 000u
TMR2IF TMR1IF
0000 0000 0000 0000
CCP3IF CCP2IF
000- 0-00 000- 0-00
TMR2IE TMR1IE
0000 0000 0000 0000
CCP3IE CCP2IE
000- 0-00 000- 0-00
xxxx xxxx uuuu uuuu
CHS3
PCFG1
RA1
RE1
ADON
PCFG0
RA0
RE0
ADRESH A/D Result Register High Byte
CHS0 GO/DONE
PCFG3
RA3
RE3
(3)
—
(3)
PCFG2
RA2
RE2
ADCS2 VCFG1
0000 0000 0000 0000
0000 000
0000 0000
xx0x 0000 uu0u 0000
1111 1111 1111 1111
---- x000 ---- x000
0000 1111 0000 1111
PORTA Data Direction Register
PORTE Data Direction bits
x
= unknown,
u
= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
These registers are reserved on the PIC16F737/767 devices.
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
DS30498C-page 160
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
