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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览
型号: PIC16F767-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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PIC16F7X7
11.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The AUSART can be configured in the following
modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have
to be set in order to configure pins RC6/TX/CK and
RC7/RX/DT
as
the
Universal
Synchronous
Asynchronous Receiver Transmitter.
The AUSART module also has a multi-processor
communication capability using 9-bit address detection.
The Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART) module is one of the
two serial I/O modules. (AUSART is also known as a
Serial Communications Interface or SCI.) The AUSART
can be configured as a full-duplex asynchronous system
that can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 11-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit 7
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit 0
bit 7
CSRC:
Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1
= Master mode (clock generated internally from BRG)
0
= Slave mode (clock from external source)
TX9:
9-bit Transmit Enable bit
1
= Selects 9-bit transmission
0
= Selects 8-bit transmission
TXEN:
Transmit Enable bit
1
= Transmit enabled
0
= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
SYNC:
AUSART Mode Select bit
1
= Synchronous mode
0
= Asynchronous mode
Unimplemented:
Read as ‘0’
BRGH:
High Baud Rate Select bit
Asynchronous mode:
1
= High speed
0
= Low speed
Synchronous mode:
Unused in this mode.
TRMT:
Transmit Shift Register Status bit
1
= TSR empty
0
= TSR full
TX9D:
9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
2004 Microchip Technology Inc.
DS30498C-page 133