PIC16CR54C
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
M
Postscaler
Postscaler
1
Watchdog
Timer
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-5:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Address
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
—
—
T0CS
T0SE
PSA
PS2
PS1
PS0
--11 1111 --11 1111
Legend: Shaded boxes = Not used by Watchdog Timer,
–= unimplemented, read as '0', u= unchanged
DS40191A-page 33
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
