PIC16CR54C
TABLE 7-3:
RESET CONDITIONS FOR SPECIAL REGISTERS
PCL
Addr: 02h
STATUS
Addr: 03h
Condition
Power-On Reset
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0001 1xxx
(1)
MCLR reset (normal operation)
MCLR wake-up (from SLEEP)
WDT reset (normal operation)
WDT wake-up (from SLEEP)
000u uuuu
0001 0uuu
(2)
0000 1uuu
0000 0uuu
Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.
Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
2: The CLRWDTinstruction will set the TO and PD bits.
TABLE 7-4:
Register
RESET CONDITIONS FOR ALL REGISTERS
Address
Power-On Reset
MCLR or WDT Reset
W
N/A
N/A
xxxx xxxx
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
111x xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
1111 1111
000q quuu
111u uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
TRIS
OPTION
INDF
TMR0
N/A
00h
01h
(1)
PCL
02h
(1)
STATUS
03h
FSR
04h
PORTA
05h
PORTB
06h
General Purpose Register Files
07-1Fh
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0',
q= see tables in Section 7.7 for possible values.
Note 1: See Table 7-3 for reset value for specific conditions.
FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
8-bit Asynch
S
R
Q
WDT
On-Chip
RC OSC
Ripple Counter
Q
(Start-Up Timer)
CHIP RESET
DS40191A-page 29
Preliminary
1998 Microchip Technology Inc.