欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16C57C-04I/SO 参数 Datasheet PDF下载

PIC16C57C-04I/SO图片预览
型号: PIC16C57C-04I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ROM的8位CMOS微控制器系列 [ROM-Based 8-Bit CMOS Microcontroller Series]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 84 页 / 641 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第24页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第25页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第26页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第27页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第29页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第30页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第31页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第32页  
PIC16CR54C  
The Electrical Specifications sections show RC  
frequency variation from part to part due to normal  
process variation. The variation is larger for larger R  
(since leakage current variation will affect RC  
frequency more for large R) and for smaller C (since  
variation of input capacitance will affect RC frequency  
more).  
7.3  
Reset  
PIC16CR54C devices may be reset in one of the  
following ways:  
• Power-On Reset (POR)  
• MCLR reset (normal operation)  
• MCLR wake-up reset (from SLEEP)  
• WDT reset (normal operation)  
• WDT wake-up reset (from SLEEP)  
Also, see the Electrical Specifications sections for  
variation of oscillator frequency due to VDD for given  
Rext/Cext values as well as frequency variation due to  
operating temperature for given R, C, and VDD values.  
Table 7-3 shows these reset conditions for the PCL  
and STATUS registers.  
The oscillator frequency, divided by 4, is available on  
the OSC2/CLKOUT pin, and can be used for test  
purposes or to synchronize other logic.  
Some registers are not affected in any reset condition.  
Their status is unknown on POR and unchanged in  
any other reset. Most other registers are reset to a  
“reset state” on Power-On Reset (POR), MCLR or  
WDT reset. A MCLR or WDT wake-up from SLEEP  
also results in a device reset, and not a continuation of  
operation before SLEEP.  
FIGURE 7-6: RC OSCILLATOR MODE  
VDD  
Rext  
Internal  
clock  
OSC1  
N
The TO and PD bits (STATUS <4:3>) are set or  
cleared depending on the different reset conditions  
(Section 7.7). These bits may be used to determine  
the nature of the reset.  
Cext  
VSS  
PIC16CR54C  
Table 7-4 lists a full description of reset states of all  
registers. Figure 7-7 shows a simplified block diagram  
of the on-chip reset circuit.  
Fosc/4  
OSC2/CLKOUT  
Note:  
If you change from this device to  
another device, please verify oscillator  
characteristics in your application.  
DS40191A-page 28  
Preliminary  
1998 Microchip Technology Inc.  
 复制成功!