PIC16F7X7
FIGURE 1-1:
PIC16F737 AND PIC16F767 BLOCK DIAGRAM
PORTA
RA0/AN0
RA1/AN1
13
8
Data Bus
Program Counter
Standard
Flash
Program
Memory
4K/8K x 14
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/
SS/C2OUT
RAM
File
Registers
8-Level Stack
(13-bit)
OSC2/CLKO/RA6
OSC1/CLKI/RA7
368 x 8
Program
Bus
14
RAM Addr(1)
PORTB
9
RB0/INT/AN12
RB1/AN10
Addr MUX
Instruction Register
RB2/AN8
Indirect
Addr
7
Direct Addr
RB3/CCP2(1)/AN9
RB4/AN11
8
FSR reg
RB5/AN13/CCP3
RB7/PGD:RB6/PGC
Status reg
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
RC6/TX/CK
RC7/RX/DT
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
WREG
OSC1/CLKI
OSC2/CLKO
Brown-out
Reset
PORTE
VDD, VSS
MCLR/VPP/RE3
Timer0
Timer1
Timer2
MSSP
10-bit A/D
Addressable
USART
BOR/LVD
Comparators
CCP1, 2, 3
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
DS30498C-page 6
2004 Microchip Technology Inc.