PIC16F7X7
Pin Diagrams (Continued)
PDIP (40-pin)
MCLR/VPP/RE3
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RB5/AN13/CCP3
RB4/AN11
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RB3/CCP2(1)/AN9
RB2/AN8
RA5/AN4/LVDIN/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB1/AN10
RB0/INT/AN12
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
TQFP (44-pin)
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/LVDIN/SS/C2OUT
RA4/T0CKI/C1OUT
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
PIC16F747
PIC16F777
VDD
RB0/INT/AN12
RB1/AN10
RB2/AN8
9
10
11
25
24
23
RB3/CCP2(1)/AN9
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2004 Microchip Technology Inc.
DS30498C-page 3