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PIC16F777-I/PT 参数 Datasheet PDF下载

PIC16F777-I/PT图片预览
型号: PIC16F777-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
FIGURE 5-18:  
PORTD BLOCK DIAGRAM  
(IN I/O PORT MODE)  
5.4  
PORTD and TRISD Registers  
This section is not applicable to the PIC16F737 or  
PIC16F767.  
Data Bus  
WR Port  
D
Q
PORTD is an 8-bit port with Schmitt Trigger input  
buffers. Each pin is individually configureable as an  
input or output.  
I/O pin(1)  
CK  
Data Latch  
PORTD can be configured as an 8-bit wide micro-  
processor port (Parallel Slave Port) by setting control  
bit, PSPMODE (TRISE<4>). In this mode, the input  
buffers are TTL.  
D
Q
Schmitt  
Trigger  
Input  
WR TRIS  
RD TRIS  
CK  
TRIS Latch  
Buffer  
Q
D
EN  
RD Port  
Note 1: I/O pins have protection diodes to VDD and VSS.  
TABLE 5-7:  
Name  
PORTD FUNCTIONS  
Bit#  
Buffer Type  
Function  
RD0/PSP0  
RD1/PSP1  
RD2/PSP2  
RD3/PSP3  
RD4/PSP4  
RD5/PSP5  
RD6/PSP6  
RD7/PSP7  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
ST/TTL(1)  
Input/output port pin or Parallel Slave Port bit 0.  
Input/output port pin or Parallel Slave Port bit 1.  
Input/output port pin or Parallel Slave Port bit 2.  
Input/output port pin or Parallel Slave Port bit 3.  
Input/output port pin or Parallel Slave Port bit 4.  
Input/output port pin or Parallel Slave Port bit 5.  
Input/output port pin or Parallel Slave Port bit 6.  
Input/output port pin or Parallel Slave Port bit 7.  
Legend: ST = Schmitt Trigger input, TTL = TTL input  
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.  
TABLE 5-8:  
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD  
Value on  
all other  
Resets  
Value on:  
POR, BOR  
Address  
Name  
Bit 7 Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
08h  
PORTD  
TRISD  
TRISE  
RD7  
RD6  
RD5  
RD4  
RD3  
RD2  
RD1  
RD0  
xxxx xxxx uuuu uuuu  
1111 1111 1111 1111  
0000 1111 0000 1111  
88h  
PORTD Data Direction Register  
IBF OBF IBOV PSPMODE  
(1)  
89h  
PORTE Data Direction bits  
Legend:  
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.  
Note 1: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.  
2004 Microchip Technology Inc.  
DS30498C-page 67  
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