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PIC16F777-I/PT 参数 Datasheet PDF下载

PIC16F777-I/PT图片预览
型号: PIC16F777-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
FIGURE 5-17:  
PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
OVERRIDE) RC<4:3> PINS  
5.3  
PORTC and the TRISC Register  
PORTC is an 8-bit wide, bidirectional port. The corre-  
sponding data direction register is TRISC. Setting a  
TRISC bit (= 1) will make the corresponding PORTC  
pin an input (i.e., put the corresponding output driver in  
a high-impedance mode). Clearing a TRISC bit (= 0)  
will make the corresponding PORTC pin an output (i.e.,  
put the contents of the output latch on the selected pin).  
Port/Peripheral Select(2)  
Peripheral Data Out  
Data Bus  
0
VDD  
D
Q
P
I/O  
WR  
Port  
pin(1)  
1
PORTC is multiplexed with several peripheral functions  
(Table 5-5). PORTC pins have Schmitt Trigger input  
buffers.  
Q
CK  
Data Latch  
D
Q
Q
WR  
When enabling peripheral functions, care should be  
taken in defining TRIS bits for each PORTC pin. Some  
peripherals override the TRIS bit to make a pin an  
output, while other peripherals override the TRIS bit to  
make a pin an input. Since the TRIS bit override is in  
effect while the peripheral is enabled, read-modify-  
write instructions (BSF, BCF, XORWF) with TRISC as  
destination should be avoided. The user should refer to  
the corresponding peripheral section for the correct  
TRIS bit settings and to Section 16.1 “Read-Modify-  
Write Operations” for additional information on  
read-modify-write operations.  
TRIS  
CK  
N
TRIS Latch  
Vss  
RD  
TRIS  
Schmitt  
Trigger  
Peripheral  
OE(3)  
Q
D
Schmitt  
Trigger  
EN  
with  
RD  
Port  
SMBus  
Levels  
0
SSPl Input  
1
FIGURE 5-16:  
PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
OVERRIDE) RC<2:0>,  
RC<7:5> PINS  
CKE  
SSPSTAT<6>  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral Select signal selects between port data  
and peripheral output.  
Port/Peripheral Select(2)  
3: Peripheral OE (Output Enable) is only activated if  
Peripheral Select is active.  
Peripheral Data Out  
Data Bus  
VDD  
P
0
1
D
Q
I/O  
WR  
pin(1)  
Port  
CK  
Q
Data Latch  
D
Q
Q
WR  
TRIS  
CK  
N
TRIS Latch  
VSS  
RD  
TRIS  
Schmitt  
Trigger  
Peripheral  
OE(3)  
Q
D
EN  
RD  
Port  
Peripheral Input  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral Select signal selects between port  
data and peripheral output.  
3: Peripheral OE (Output Enable) is only activated if  
Peripheral Select is active.  
2004 Microchip Technology Inc.  
DS30498C-page 65  
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