PIC16F7X7
FIGURE 5-21:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-22:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
Resets
Value on:
POR, BOR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
PORTD Port Data Latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- x000 ---- x000
0000 1111 0000 1111
09h
PORTE
TRISE
PIR1
—
IBF
—
—
—
RE3
RE2
RE1
RE0
(2)
89h
OBF
ADIF
ADIE
IBOV PSPMODE
—
PORTE Data Direction bits
(1)
(1)
0Ch
PSPIF
PSPIE
RCIF
RCIE
TXIF
TXIE
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Ch
PIE1
9Fh
ADCON1 ADFM ADCS2 VCFG1 VCFG0
PCFG3 PCFG2 PCFG1 PCFG0
0000 0000 0000 0000
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767; always maintain these bits clear.
2: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS30498C-page 71
MICROCHIP [ MICROCHIP ]
