PIC16F7X7
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR, BOR on page
Details
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
(4)
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
101h
TMR0
Timer0 Module Register
xxxx xxxx 76, 180
0000 0000 29, 180
0001 1xxx 21, 180
xxxx xxxx 30, 180
(4)
102h
PCL
Program Counter (PC) Least Significant Byte
(4)
103h
STATUS
FSR
IRP
Indirect Data Memory Address Pointer
WDTPS3
RP1
RP0
TO
PD
Z
DC
C
(4)
104h
105h
106h
107h
108h
109h
WDTCON
PORTB
—
—
—
—
WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
187
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 64, 180
Unimplemented
Unimplemented
—
—
—
—
—
LVDCON
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
—
—
—
—
IRVST
—
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101
176
(1,4)
10Ah
Write Buffer for the upper 5 bits of the Program Counter
INT0IE RBIE TMR0IF INT0IF RBIF
---0 0000 23, 180
0000 000x 25, 180
xxxx xxxx 32, 181
xxxx xxxx 32, 181
--xx xxxx 32, 181
---- xxxx 32, 181
(4)
10Bh
GIE
PEIE
TMR0IE
10Ch
10Dh
10Eh
10Fh
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
—
—
—
—
EEPROM Data Register High Byte
EEPROM Address Register High Byte
—
—
Bank 3
(4)
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
181h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 22, 180
0000 0000 29, 180
0001 1xxx 21, 180
xxxx xxxx 30, 180
(4)
182h
PCL
STATUS
FSR
—
(4)
183h
PD
Z
DC
C
(4)
184h
Indirect Data Memory Address Pointer
Unimplemented
185h
186h
187h
188h
189h
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 64, 181
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
(1,4)
18Ah
PCLATH
INTCON
PMCON1
—
—
—
PEIE
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 23, 180
0000 000x 25, 180
1--- ---0 32, 181
(4)
18Bh
GIE
INT0IE
—
RBIE
—
TMR0IF
—
INT0IF
—
RBIF
RD
(6)
18Ch
18Dh
18Eh
18Fh
r
Reserved, maintain clear
Reserved, maintain clear
Reserved, maintain clear
—
—
—
—
—
—
—
—
Legend: x= unknown, u= unchanged, q= value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
DS30498C-page 20
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
