PIC16F7X7
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR, BOR on page
Details
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
(4)
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
81h
OPTION_REG RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 22, 180
0000 0000 29, 180
0001 1xxx 21, 180
xxxx xxxx 30, 180
1111 1111 55, 181
1111 1111 64, 181
1111 1111 66, 181
1111 1111 67, 181
0000 1111 69, 181
---0 0000 23, 180
0000 000x 25, 180
(4)
82h
PCL
Program Counter’s (PC) Least Significant Byte
(4)
83h
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
(4)
84h
Indirect Data Memory Address Pointer
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
85h
86h
87h
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
(5)
88h
(5)
(5)
(5)
(5)
(5)
(8)
89h
IBF
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction bits
(1,4)
8Ah
—
GIE
Write Buffer for the upper 5 bits of the Program Counter
(4)
8Bh
PEIE
ADIE
CMIE
—
TMR0IE
RCIE
INT0IE
TXIE
—
RBIE
SSPIE
BCLIE
—
TMR0IF
INT0IF
RBIF
(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
PSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 24, 181
PIE2
OSFIE
—
LVDIE
—
—
SBOREN
IOFS
CCP3IE CCP2IE 000- 0-00 26, 181
PCON
—
POR
SCS1
TUN1
RSEN
BOR
SCS0
TUN0
SEN
---- -1qq 28, 181
-000 1000 38, 181
--00 0000 36, 181
(7)
OSCCON
OSCTUNE
SSPCON2
PR2
—
IRCF2
—
IRCF1
TUN5
ACKDT
IRCF0
TUN4
ACKEN
OSTS
TUN3
RCEN
—
TUN2
PEN
GCEN ACKSTAT
0000 0000
105
Timer2 Period Register
1111 1111 86, 181
0000 0000 101, 181
2
SSPADD
Synchronous Serial Port (I C™ mode) Address Register
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPSTAT
CCPR3L
CCPR3H
CCP3CON
TXSTA
SMP
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
CKE
D/A
P
S
R/W
UA
BF
0000 0000 101, 181
xxxx xxxx
xxxx xxxx
92
92
92
—
—
CCP3X
TXEN
CCP3Y
SYNC
CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000
CSRC
TX9
—
BRGH
TRMT
TX9D
0000 -010 145, 181
0000 0000 145, 181
SPBRG
—
Baud Rate Generator Register
Unimplemented
—
—
ADCON2
CMCON
CVRCON
ADRESL
ADCON1
—
—
ACQT2
C2INV
CVRR
ACQT1
C1INV
—
ACQT0
CIS
—
—
—
--00 0---
154
C2OUT
CVREN
C1OUT
CVROE
CM2
CVR2
CM1
CVR1
CM0
CVR0
0000 0111 55, 161
000- 0000 55, 167
CVR3
A/D Result Register Low Byte
ADFM ADCS2 VCFG1
xxxx xxxx
180
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 0000 0000 153, 181
Legend: x= unknown, u= unchanged, q= value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS30498C-page 19
MICROCHIP [ MICROCHIP ]
