PIC16F7X7
10.3.8
SLEEP OPERATION
10.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 10-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 10-1: SPI™ BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
Control Bits State
Standard SPI™
Mode Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
10.3.9
EFFECTS OF A RESET
There is also an SMP bit which controls when the data
is sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 10-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
TMR0IF
CCP1IF
CCP1IE
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
TMR2IF TMR1IF 0000 0000 0000 0000
TMR2IE TMR1IE 0000 0000 0000 0000
1111 1111 1111 1111
(1)
PIE1
TRISC
PORTC Data Direction Register
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON
TRISA
WCOL
PORTA Data Direction Register
SMP CKE D/A
SSPOV
SSPEN
CKP
SSPM3
SSPM2
R/W
SSPM1
UA
SSPM0 0000 0000 0000 0000
1111 1111 1111 1111
SSPSTAT
Legend:
P
S
BF
0000 0000 0000 0000
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
Note 1: The PSPIF and PSPIE bits are reserved on 28-pin devices; always maintain these bits clear.
2004 Microchip Technology Inc.
DS30498C-page 101
MICROCHIP [ MICROCHIP ]
