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Applicable Devices 710 71 711 715
TABLE 15-6: A/D CONVERTER CHARACTERISTICS
Param Sym Characteristic
No.
Min
Typ†
—
Max
8 bits
< ±1
Units
Conditions
A01
NR Resolution
—
bits VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02
EABS Absolute error
—
—
LSb VREF = VDD = 5.12V,
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VSS ≤ VAIN ≤ VREF
—
—
—
—
< ±2
< ±1
LSb VREF = VDD = 3.0V (Note 3)
A03
A04
A05
A06
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
—
—
< ±2
< ±1
LSb VREF = VDD = 3.0V (Note 3)
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
—
—
< ±2
< ±1
LSb VREF = VDD = 3.0V (Note 3)
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
—
—
< ±2
< ±1
LSb VREF = VDD = 3.0V (Note 3)
EOFF Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
—
< ±2
—
LSb VREF = VDD = 3.0V (Note 3)
A10
A20
A25
A30
—
Monotonicity
guaranteed
—
V
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
VAIN Analog input voltage
3.0V
VSS - 0.3
—
—
—
—
VDD + 0.3
VREF
V
ZAIN Recommended impedance of analog
voltage source
10.0
kΩ
A40
A50
IAD A/D conversion current (VDD)
—
180
—
—
µA Average current consump-
tion when A/D is on. (Note 1)
IREF VREF input current (Note 2)
10
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
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To charge CHOLD see
Section 7.1.
—
—
—
—
40
1
µA During A/D Conversion cycle
mA During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
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To charge CHOLD see
Section 7.1.
—
—
10
µA During A/D Conversion cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VAIN must be between VSS and VREF.
1997 Microchip Technology Inc.
DS30272A-page 145